Field programmable gate arrays (FPGA) are integrated circuits that may be configured, or programmed, by the user to form complex logic circuits. Programming is performed after the FPGA is manufactured, generally at the site of the purchaser, or "in the field." FPGA's provide many of the advantages of custom integrated circuits, such as complex functions in a single package, low power consumption, etc. Small quantities of such circuits can be created using FPGA's much less expensively than a custom integrated circuit. FPGAs combine the flexibility of mask programmable gate arrays with the convenience of field programmability.
FPGA's have two primary elements: (1) a two dimensional array of universal logic modules and (2) a corresponding array of programmable interconnects to form the selective programmable connections between the logic modules. The universal logic modules are made up of a number of functional devices such as diodes, transistors, logic gates, multiplexers, and the like. The logic modules are interconnected by selectively programming the programmable interconnects to establish connections between the outputs of one logic module and the inputs of other logic modules. The programmable interconnects may be fuses, antifuses, or other means. Signals generated external to the FPGA are also connected by programmable interconnects to the inputs of various logic modules. Output signals from selected logic modules may be connected by programmable interconnects to outputs of the FPGA. The output of each logic module is a logical combination of the inputs of that logic module and may correspond to, for example, digital logic devices such as NAND gates, AND gates, and OR gates. A typical logic module will have approximately eight inputs and can be connected so that any one of several hundred boolean combinations of one to eight input signals is produced at the output.
Prior art FIG. 1 shows a portion of a typical FPGA 100. Six logic modules 101 are shown, arranged in two rows of three. The array size of a typical FPGA may be 12 by 40, for example, or larger. Each logic module 101 has a plurality of inputs, such as inputs 102a-102h and an output, such as output 104. An interconnect network comprising vertical tracks and horizontal tracks may be selectively configured by programming fuses or antifuses, as described in U.S. Pat. No. 5,166,557 Gate Array with Built-in Programming Circuitry, to interconnect the logic modules. The horizontal tracks are typically broken into smaller segments to allow flexibility in establishing the selected connections.
Still referring to prior art FIG. 1, a plurality of external input signals may be connected to a plurality of external pins, such as pin 116, buffered by receivers, such as receiver 118, and placed on horizontal track segments, such as segment 112a. Horizontal segment 112a may be connected to horizontal segment 114a by programming antifuse 108 to be conductive. Other horizontal segments may be similarly interconnected. One of a plurality of horizontal track segments 112a-112d may be selectively connected to the logic module inputs, such as input 102a, by programming one of antifuses 106a-106d to be conductive. Each logic module 101 has an output, such as output 104, connected to a vertical track, such as track 110. Output 104 may be connected to a plurality of horizontal segments, such as segments 112a-112dand segments 124a-124d, by programming any of antifuses 107a-107dand 109a-109d, respectively, to be conductive. A plurality of output drivers, such as driver 122, connect to a plurality of output pins, such as pin 120, to drive a plurality of external signals.
Prior art FIG. 2 shows FPGA logic module 101 comprising multiplexers 210, 212, 214, AND gate 216 and NOR gate 218. Various combinational results of signals placed on input terminals 102a-102hcan be formed and placed on output terminal 104, for example: 102e AND 102f, 102e AND 102f AND 102d, 102g NOR 102h, etc, as is well understood to those skilled in the art. Typically, approximately several hundred logical combinations of input terminals 102a-102h can be formed.
Prior art FIG. 3 shows an FPGA logic module 300 which is comprised of logic module 101, of the type illustrated in FIG. 2, connected to logic module 302. Logic module 302 typically provides a latch and/or flipflop function which allows the signal leaving module 101 to be either latched or passed through without being latched. Control signals 304a and 304b control what function module 302 performs. The end result is that logic module 300 can be reconfigured to perform various combinational logic functions or a sequential latch function.
When a FPGA of the type illustrated in FIG. 3 is used to implement a complex logic circuit, portions of the logic circuit typically require combinational logic functions, while other portions of the logic circuit typically require sequential logic functions. However, if logic module 300 is used as a combinational logic function, then module 302 may be essentially unused. Likewise, if logic module 300 is used as a sequential latch function, then logic module 101 may not always be used. Space on the FPGA may be wasted since large amounts of logic modules may not be usable in any given application. Furthermore, several logic modules 300 may be needed to create commonly used logic functions, such as an adder, thereby undesirably reducing the maximum size of a logic circuit that can be created on a single FPGA 100 by the user.
Accordingly, it is an object of the invention to create a logic module that uses less space so that more logic modules can be placed in a given FPGA.
Another object of the invention is to create a logic module that is capable of performing more logic functions than prior art modules.
Other objects and advantages will be apparent to those of ordinary skill in the art having reference to the following figures and specification.